March 08, 2020

FPGA Implementation of Deep Neural Network Based Equalizers for High-Speed PON

  • Bergman K.
  • Chuang C.
  • Farah B.
  • Houtsma V.
  • Kaneda N.
  • Mahadevan A.
  • Veen D.
  • Zhu Z.

A fixed-point deep neural network-based equalizer is implemented in FPGA and is shown to outperform MLSE in receiver sensitivity for 50 Gb/s PON downstream link. Embedded parallelization is proposed and verified to reduce hardware resources.

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Recent Publications

May 01, 2020

A Packaged 0.01-26-GHz Single-Chip SiGe Reflectometer for Two-Port Vector Network Analyzers

  • Chung H.
  • Ma Q.
  • Rebeiz G.
  • Sayginer M.

© 1963-2012 IEEE. This article presents a packaged SiGe BiCMOS reflectometer for 0.01-26-GHz two-port vector network analyzers (VNAs). The reflectometer chip is composed of a resistive bridge coupler and two wideband heterodyne receivers for coherent magnitude and phase detection. In addition, a high-linearity receiver channel is designed to accommodate 20 ...

August 01, 2019

Protecting photonic quantum states using topology

  • Blanco-Redondo A.

The use of topology to protect quantum information is well-known to the condensed-matter community and, indeed, topological quantum computing is a bursting field of research and one of the competing avenues to demonstrate that quantum computers can complete certain problems that classical computers cannot. In photonics, however, we are only ...

May 01, 2019

Digital networks at the nexus of productivity growth

  • Kamat S.
  • Prakash S.
  • Saniee I.
  • Weldon M.

This paper takes a fresh look at the debate over the relationship between digital technology and productivity. The argument of economic historian Robert J. Gordon is that digital technology will not lead to increases in productivity such as we saw in the last century, based on his analysis of the ...