Real-time implementation of high-speed digital coherent transceivers
- Pfau T.
The real-time implementation of digital coherent receivers for 100 Gbit/s data rates and beyond pushes the limits of all the technologies involved. Digital-to-analog and analog-to-digital converters with ultra-high sampling rates need to be co-integrated with a large scale digital signal processing (DSP) engine, and highly sophisticated algorithms have to be mapped into digital logic with the best compromise between performance and power consumption. This chapter describes the main constraints put on the DSP algorithms by the hardware structure, and gives a brief overview on technologies and challenges for prototype and commercial real-time implementations of coherent receivers.