_imported_https://media-bell-labs-com.s3.amazonaws.com/bell_labs/users/2015/02/25/dsc_0180_Modified.jpg

Souradip Sarkar

Antwerp, Belgium

Research Interests

Education

1) Washington State University, Ph.D, Electrical Engineering, 2010.
2) Washington State University, M.S., Computer Engineering, 2007.
3) Indian Statistical Institute, M. Tech., Computer Science, 2006.

 

 

Selected articles and publications

1. NoC-Based Hardware Accelerator for Breakpoint Phylogeny. IEEE Trans. Computers 61(6): 857-869 (2012)
2. Power-aware multi-core simulation for early design stage hardware/software co-optimization,  PACT 2012: 3-12
3. Using Fast and Accurate Simulation to Explore Hardware/Software Trade-offs in the Multi-Core Era. PARCO 2011: 343-350
4. Network-on-Chip Hardware Accelerators for Biological Sequence Alignment. IEEE Trans. Computers 59(1): 29-41 (2010)
5. An optimized NoC architecture for accelerating TSP kernels in breakpoint median problem. ASAP 2010: 89-96
6. Hardware accelerators for biocomputing: A survey. ISCAS 2010: 3789-3792
7. Multiple clock domain synchronization for network on chip architectures. SoCC 2007: 291-294