Picture of Manil Dev Gomony

Manil Dev Gomony

Antwerp, Belgium
Digital FPGA/ASIC Researcher

Education

­PhD in Electrical Engineering, Eindhoven University of Technology, The Netherlands, 2015: Research areas include modeling, design and optimization of memory subsystems and interconnect architectures for high-performance embedded real-time systems.


MSc. in Electrical Engineering, Linköping University, Sweden, 2010: Specialization on System-on-Chip (SoC) design


BTech in Applied Electronics & Instrumentation Engineering, College of Engineering Trivandrum, India, 2002

 

 

 

Biography

­Joined Alcatel-Lucent Bell Labs in December 2014: Reasearch areas include design methodologies for fast prototyping of hardware accelerators, application-specific processors

Obtained PhD in Electrical Engineering from Eindhoven University of Technology in 2015

­Internship at NEC Laboratories Europe, 2009: Invented a novel method for power saving and QoS optimization in WLAN 802.11n.

­Worked as an embedded software engineer in Robert Bosch India, 2004-07, 2010: Designed and developed firmware for power management, device drivers and schedulers for multimedia and cyber-physical systems.

 

Research Interests

  • Network Architecture & Design

Professional Activities

Organizing committee of ASCI GNARP Workshop 2014

Served as an external/additional reviewer for the following journals and conferences: TVLSI, ACM TECS, COMPJ, IJERTCS, JCST, DAC, DATE, CODES+ISSS, CASES, FPL, ICCD, ECRTS, SoC, RTAS


Selected Articles and Publications


A Globally Arbitrated Memory Tree for Mixed-Time-Criticality Systems; Manil Dev Gomony, Jamie Garside, Benny Akesson, Neil Audsley, & Kees Goossens; in IEEE Transactions on Computers, vol. , no. , pp. 1, 5555, doi:10.1109/TC.2016.2595581

A Generic, Scalable and Globally Arbitrated Memory Tree for Shared DRAM Access in Real-Time Systems; Manil Dev Gomony, Jamie Garside, Benny Akesson, Neil Audsley, & Kees Goossens; in Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE) 2015

A Real-Time Multi-Channel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels; Manil Dev Gomony, Benny Akesson, & Kees Goossens; ACM Transactions on Embedded Computing Systems (TECS), 14(2) 2015

Coupling TDM NoC and DRAM Controller for Cost and Performance Optimization of Real-Time Systems; Manil Dev Gomony, Benny Akesson, & Kees Goossens; in Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE) 2014

Architecture and Optimal Configuration of a Real-Time Multi-Channel Memory Controller; Manil Dev Gomony, Benny Akesson, & Kees Goossens; in Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE) 2013

DRAM Selection and Configuration for Real-Time Mobile Systems; Manil Dev Gomony, Christian Weis, Benny Akesson, Nobert Wehn & Kees Goossens; in Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE) 2012

 

 

 

 

 

Patents

Method for operating a wireless network and a wireless network. US Patent App. 13/574,320.