A 7b 1.25GS/s 3.8mW Single-Channel SAR ADC with a Triple-Tail Comparator, Improved T/H and Unit-Switch-Plus-Cap-DAC achieving 36.4dB SNDR at 5GHz Input Frequency

  • Pelgrom Marcel
  • Ramkaj A.
  • Steyaert M.
  • Strackx M.
  • Tavernier F.

To support continuous bandwidth growth of next-generation high-speed serial links, moderate-resolution energy-efficient gigahertz-sampling-rate ADCs are highly demanded. SAR ADCs bare an excellent power-efficiency due to their highly digitized nature, allowing them to scale proficiently into deep-submicron nodes. Several techniques have been presented recently to increase SAR speed such as capacitive DAC (CDAC) redundancy and alternate comparators, interleaving schemes, multi-bit per step decisions and interrupted settling. This work addresses the demand for a fast, low-power SAR ADC, with a compact single-channel converter achieving 1.25GS/s and 5GHz bandwidth by using a triple-tail comparator, improved T/H design, and optimal CDAC implementation. As such, the hardware and complexity problems of multi-bit per step, redundancy and alternate comparators techniques, as well as interleaving artifacts are alleviated. The proposed ADC achieves 40.08dB SNDR at Nyquist with 3.8mW from 1V supply, leading to a FoM of 36.95fJ/conv-step for a core chip area of 0.0071mm2, while SNDR remains 36.4dB at 5GHz input frequency.

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