A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW SAR ADC Using Switch-Bootstrapping, Unit-Switch-Plus-Cap DAC and Triple-Tail Comparator in 28nm Bulk CMOS

  • Ramkaj A.
  • Steyaert M.
  • Strackx M.
  • Tavernier F.

A 1.25GS/s 7b single-channel SAR ADC is presented with an SNDR/SFDR of 41.4dB/51dB at low frequencies, while the SNDR/SFDR at Nyquist are 40.1dB/52dB and are still 36.4dB/50.1dB at 5GHz. The high input frequency linearity is enabled by a fast bootstrap circuit for the input switch, while the high sampling rate, the highest among recently published >34dB SNDR single-channel SARs is achieved by a Triple-Tail dynamic comparator and a Unit-Switch-Plus-Cap (USPC) DAC. The prototype ADC in 28nm CMOS consumes 3.56mW from a 1V supply, leading to a Walden FoM of 34.4fJ/conv-step for a core chip area of 0.0071mm2.

Recent Publications

August 01, 2019

Protecting photonic quantum states using topology

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The use of topology to protect quantum information is well-known to the condensed-matter community and, indeed, topological quantum computing is a bursting field of research and one of the competing avenues to demonstrate that quantum computers can complete certain problems that classical computers cannot. In photonics, however, we are only ...

May 01, 2019

Digital networks at the nexus of productivity growth

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This paper takes a fresh look at the debate over the relationship between digital technology and productivity. The argument of economic historian Robert J. Gordon is that digital technology will not lead to increases in productivity such as we saw in the last century, based on his analysis of the ...

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© 2017 International World Wide Web Conference Committee (IW3C2), published under Creative Commons CC BY 4.0 License. Many of today's websites have recognised the importance of mobile friendly pages to keep users engaged and to provide a satisfying user experience. However, next to the experience provided by the sites themselves, ...