A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW SAR ADC Using Switch-Bootstrapping, Unit-Switch-Plus-Cap DAC and Triple-Tail Comparator in 28nm Bulk CMOS
- Ramkaj A.
- Steyaert M.
- Strackx M.
- Tavernier F.
A 1.25GS/s 7b single-channel SAR ADC is presented with an SNDR/SFDR of 41.4dB/51dB at low frequencies, while the SNDR/SFDR at Nyquist are 40.1dB/52dB and are still 36.4dB/50.1dB at 5GHz. The high input frequency linearity is enabled by a fast bootstrap circuit for the input switch, while the high sampling rate, the highest among recently published >34dB SNDR single-channel SARs is achieved by a Triple-Tail dynamic comparator and a Unit-Switch-Plus-Cap (USPC) DAC. The prototype ADC in 28nm CMOS consumes 3.56mW from a 1V supply, leading to a Walden FoM of 34.4fJ/conv-step for a core chip area of 0.0071mm2.